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Date: 2017
Language: eng
Resource Type: journal article
Identifier: http://hdl.handle.net/1959.14/1248256
Description: This article proposes a novel architecture to perform modular multiplication in the Residue Number System (RNS) by using sum of residues. The highly parallel architecture is implemented using VHDL and ... More
Reviewed: Reviewed
Date: 2014
Language: eng
Resource Type: conference paper
Identifier: http://hdl.handle.net/1959.14/337938
Description: This paper presents a low-cost Finite Impulse Response (FIR) filter architecture for Discrete Wavelet Transform (DWT) using Residue Number System (RNS) arithmetic blocks. Modular adders and multiplier ... More
Reviewed: Reviewed
Date: 2012
Language: eng
Resource Type: journal article
Identifier: http://hdl.handle.net/1959.14/206352
Description: 8 page(s)
Reviewed: Reviewed
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