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Date: 2017
Language: eng
Resource Type: journal article
Identifier: http://hdl.handle.net/1959.14/1248256
Description: This article proposes a novel architecture to perform modular multiplication in the Residue Number System (RNS) by using sum of residues. The highly parallel architecture is implemented using VHDL and ... More
Reviewed: Reviewed
Date: 2015
Language: eng
Resource Type: conference paper
Identifier: http://hdl.handle.net/1959.14/1067003
Description: Wallace tree multipliers provide a power-efficient strategy for high speed multiplication. The use of high speed 7?3 counters in the Wallace tree reduction can further improve the multiplier speed. Th ... More
Reviewed: Reviewed
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